The present invention relates generally to semiconductor processing, and in particular to a system for adjusting exposure conditions before exposing a pattern on a wafer layer.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as coiners and edges, of various features. When feature sizes become smaller, ensuring that pattern exposure conditions will produce a pattern with desired critical dimensions on a wafer becomes more important.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The precision with which the electrically active regions can be created is important in achieving desired critical dimensions in the chips. Such precision is affected by the ability to control pattern exposure conditions. If the exposure conditions are such that exposing a pattern will not produce desired critical dimensions, then the electrically active regions may not operate together properly, thus reducing chip manufacturing efficiency and chip quality. Exposure conditions including focus depth, focus width and dose can effect such the critical dimensions that will be achieved when a pattern is exposed.
The requirement of small features with close spacing between adjacent features requires sophisticated manufacturing techniques, including high-resolution photolithographic processes, and calculating exposure conditions before exposing a pattern. Fabricating a semiconductor using such sophisticated techniques may involve a series of steps including cleaning, thermal oxidation or deposition, exposure condition, masking, developing, baking and doping of several layers, each of which must be formed properly to achieve desired critical dimensions. One or more patterns may be exposed on several layers formed (e.g., deposited and/or grown) on a wafer. Each such pattern may be affected by variations in a wafer (e.g., center to edge variations). Thus, exposure conditions (e.g., focus, dose) that can be employed to expose a first pattern on a first layer and achieve acceptable critical dimensions, may not be similarly achieve acceptable critical dimensions for a second pattern on a second layer. Uniformity of critical dimensions between layers can improve IC quality leading to higher clocking speeds and resulting improved performance for such ICs.
Wafers may be pre-cleaned using, for example, high-purity, low-particle chemicals. The silicon wafers may be heated and exposed to ultra-pure oxygen in diffusion furnaces under carefully controlled conditions to form a silicon dioxide film of uniform thickness on the surface of the wafer. The masking step is used to protect one area of the wafer while working on another. This process is referred to as photolithography or photo masking. A photo resist, or light-sensitive film, is applied to the wafer, giving it characteristics similar to a piece of photographic paper. A photo aligner aligns the wafer to a mask, and then projects an intense light through the mask and through a series of reducing lenses, exposing the photo resist with the mask pattern. The intensity of the light, the length of exposure, and the focusing of the lens affect the ability to achieve critical dimensions for a chip. Conventionally, the exposure condition calculation process has not been feedback controlled, requiring pre-calculated exposure condition steps and/or layer specific exposure condition calculation processes. Such pre-determined calculations may not produce exposure conditions that will yield desired critical dimensions, resulting in patterns that do not implement desired features within acceptable tolerances.
The portions of the light sensitive resist layer exposed to the light harden (for certain types of resist), facilitating removal of the non-hardened portions. If the exposure condition determinations prior to exposing a layer to light are not precise enough, an undesired portion of the light sensitive resist layer may be exposed to the light, disabling desired feature creation. After the exposed resist has hardened, the non-hardened portions are removed, exposing the oxide layer or other underlying layer previously deposited. Again, if the exposure condition determinations prior to exposure were not precise enough, an undesired portion of the oxide may be unprotected and thus may be removed during the etching process. The portions of the oxide layer not protected by the hardened resist layer may now be etched away, by, for example, a chemical solution or plasma gas discharge. The hardened photo resist is then removed using additional chemicals or plasma and the wafer is then inspected to ensure the image transfer from the mask to the top layer is correct.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the exposure condition determining process is a significant factor in achieving desired critical dimensions. Thus, an efficient system and/or method to monitor and control the exposure condition determination process is desired to increase fidelity in image transfer.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention nor is it intended to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system that facilitates controlling an exposure condition determination process involved in semiconductor manufacturing. Controlling the exposure conditions with runtime feedback provides superior exposure condition calculations and thus facilitates achieving desired critical dimensions, with substantial uniformity in such critical dimensions between layers. An exemplary system may employ an exposing system that includes one or more light sources arranged to project light onto one or more gratings on one or more portions of a wafer. The system may also include one or more light sensing devices (e.g., photo detector, photodiode) for detecting light reflected by, and/or allowed to pass through, the one or more gratings. The light reflected from, and/or passing through the one or more gratings is indicative of at least one parameter of the exposure condition process (e.g., focus depth, focus width, dose).
An exposing system is arranged to facilitate projecting a pattern onto a layer on a wafer. The exposing system may be, for example, a light and lens combination found in a stepper apparatus. It is to be appreciated by one skilled in the art that any suitable exposing system can be employed with the present invention. The exposing system is selectively controllable by the system to change exposure conditions including, but not limited to, focus, phase, intensity and dose. The exposure condition determinations are adapted by the system by comparing signatures generated by the light reflected and/or passed through the gratings pre-formed on the layers on a wafer to desired signatures. By comparing desired signatures to measured signatures, runtime feedback may be employed to more precisely determine exposure conditions that will facilitate achieving desired critical dimensions in the pattern to be developed on the wafer and as a result, more optimal exposure conditions are achieved, which in turn increases fidelity of image transfer. The increased fidelity can lead to achieving desired critical dimensions, and can further lead to substantial uniformity of critical dimensions between layers, which in turn facilitates achieving higher speeds in such chips.
An aspect of the present invention provides a system for analyzing and controlling pattern exposure conditions in semiconductor manufacturing. The system includes an exposing system that projects a pattern onto a wafer. The system also includes an exposer driving system that can control one or more exposure conditions in the exposing system. The exposure conditions are adapted based on signatures read from gratings formed on the wafer. The signatures can be read by the operation of a light directing system that direct light to at least one portion of the wafer and a measuring system that measures grating signatures based on light reflected from a grating. The system further includes a processor operatively coupled to the measuring system and the exposer driving system. The processor receives grating signature data from the measuring system and uses the grating signature data to control the exposer to adapt exposure conditions.
Another aspect of the present invention provides a method for analyzing and controlling pattern exposure conditions in a stepper. The method includes partitioning a wafer into portions; developing gratings in the portions; directing light onto at least one of the gratings; collecting light reflected from the grating; analyzing the reflected light to facilitate retrieving a signature associated with the grating; and controlling an exposer to adjust one or more pattern exposure conditions based on comparisons between the determined signature and a desired signature.
Yet another aspect of the present invention provides a method for regulating an exposure condition calculating process. The method includes partitioning a wafer into grid blocks; pre-exposing gratings on the wafer, the gratings positioned within the grid blocks; controlling an exposing system to maintain and/or change exposure conditions; determining the acceptability of the exposure conditions by analyzing the gratings pre-formed on the wafer; generating feedback information concerning the acceptability of the exposure conditions; transmitting the feedback information to a processor; and using the processor to coordinate control of the exposing system based, at least in part, on the feedback information.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.